Regular Expression to Verilog FSM

A tool to create hardware finite state machines for regular expression matching on byte streams.
The ouput is a tar of verilog files. Input regular expressions must be in PCRE format.
Vist about page for more information about this tool.

Note: Some PCRE features like backreferences are not supported yet

Example: abc+(def|ghi)*jkl
Example: regex_fsm